1. Field of the Invention
The present invention relates to a technology for relieving the fault memory area in a semiconductor memory device which is not correctly conductive and particularly to a redundancy relief technology for two or more semiconductor memory devices assembled in a single package.
2. Description of the Related Art
A semiconductor memory device having at least an array of memory cells arranged in a row-and-column matrix may produce a fault in units of memory cells, rows, columns, or memory blocks which consists of rows and columns. In order to increase the productivity of a storage apparatus, there hence have been proposed and known a variety of relief technologies for the fault memory areas (referred to as relief units).
One type of the known relief technologies is a redundancy relief technology. The redundancy relief technology is arranged in which an array of memory cells are accompanied with a desired number of redundancy rows or columns. This allows any fault row or column including a fault memory cell(s) or any entirely fault row or column to be replaced by the redundancy row or column. More particularly, the address of a fault row or column has been stored in a fault address storing means and read out for comparison with the input address received from the outside. When the input address corresponds to the address of the fault row or column saved in the fault address storing means, its relevant redundancy row or column can automatically be picked up for replacement.
Another redundancy relief technology may be provided as known a block redundancy relief technology where a fault memory block comprising a number of the memory cells is replaced by the redundancy block.
More particularly, the block redundancy relief technology permits the address of a fault block to be saved in each semiconductor memory device in advance, as shown in FIG. 6. In addition, as the input address has been received from the outside, its block address is compared with the address of the fault block saved in the fault address storing means. Then, when the two addresses are equal, their corresponding redundancy block is automatically selected.
The semiconductor memory device shown in FIG. 6 will now be explained which includes a group of memory blocks B1 to B4 and a redundancy block B5, assuming that the memory block B2 is a fault block. The address of the memory block B2 is saved as a fault block address in the fault address storing means 71 in advance. When the address input is received at an address buffer 72, its block address is transferred to an address matching circuit 73 where it is compared with the fault block address saved in the fault address storing means 71. When the block address in the input address corresponds to the fault block address, the action of an address decoder 74 for selecting the memory block B2 is canceled and the redundancy block select signal RS is released for selecting the redundancy block B5. If there is discrepancy between the two addresses, the address decoder 74 releases a decoded signal for selecting the memory block B2. This signal allows the selection of the block determined by the address received at the address buffer 72 and disables the redundancy block select signal RS for selection of the redundancy block. The fault address storing means 71 is implemented by a non-volatile memory which is fusible or electrically re-writable.
FIG. 7 illustrates an arrangement of the storage apparatus including a pair of semiconductor memory devices 7a and 7b, such as shown in FIG. 6, and an external controller 6. Any of the two semiconductor memory devices 7 is selectively enabled for operation. If one of the two semiconductor memory devices 7 contains two or more fault blocks, it can replace only one fault block with its single redundancy block and thus its usable memory capacity is decreased. Consequently, with the other semiconductor memory device 7 containing no fault block and remaining at no use of its redundancy block, the storage apparatus will save seven blocks to be applicable out of all the ten blocks.
Also, a further redundancy relief technology is disclosed in the form of a semiconductor memory device which includes an address translating circuit for fixedly translating the address from the fault block to the redundancy block (See Japanese Patent Laid-open Publication No. 2001-256793, for example). When receiving the address of a fault block from the outside, the disclosed semiconductor memory device instructs its address translating circuit to translate the address from the fault block to the redundancy block for selecting and permitting the redundancy block to replace the fault block. The semiconductor memory device aims to prevent the increase of the chip size due to the fuse circuit and the access time.
However, the redundancy relief technology disclosed in the Publication, No. 2001-256793, is not advantageous because no more of the fault blocks than the number of redundancy blocks prepared in each semiconductor memory device can be relieved. When any one of the semiconductor memory devices assembled in a single package contains more fault blocks than the number of redundancy blocks, the package itself will be judged and discarded as a fault package.
A modification is proposed in the form of a semiconductor memory device which includes a group of memory units, each comprising a number of memory blocks and a redundancy block, and a controller for translating the address from the fault block in each memory unit to the redundancy block (as disclosed in, e.g., Japanese Patent Laid-open Publication No. (Heisei)10-27138). The modified redundancy relief technology is designed for controlling the entire of each memory unit as a whole, where the relief action is made on the block-by-block basis.
While the semiconductor memory device disclosed in the Publication No. (Heisei)10-27138) permits the redundancy blocks saved in the other semiconductor memory devices to be effectively utilized for replacement since its controlling action is based on the entirety of each memory unit, it has however to translate the address from each of the fault blocks to the redundancy block. This will increase the access time for translating of the address and also make the redundancy relief circuit troublesome in the fabrication. Recently, since a plurality of the semiconductor memory devices are commonly assembled in a single package, it is now desired that the redundancy relief technology is improved for increasing the productivity and simplifying the algorithm of the redundancy relief.